Senior Digital IC Designer
工作內容
1. Lead project task force.
2. Learn standard/algorithm and define the IP/SOC specification and architecture.
3. IP integration, implementation, and timing closure.
4. Maintain or design new IP function blocks based on architecture specification or new feature request.
2. Learn standard/algorithm and define the IP/SOC specification and architecture.
3. IP integration, implementation, and timing closure.
4. Maintain or design new IP function blocks based on architecture specification or new feature request.
需求條件
1. Bachelor's degree in Electrical Engineering or Computer Science.
2. 5+ years SOC design, verification, or related work experience.
3. Experience in digital IP design using Verilog or SystemVerilog.
4. Experience with several chip tapeout and mass production.
5. Specific experience with industry standard development tools is required.
6. Solid understanding of complete SOC design flow and design techniques and methods
Preferred qualifications:
1. Master's degree in Electrical Engineering or Computer Science.
2.Experience with architecture, specification definition, task force leading, project leading.
3. Experience with SOC flow building
4.Experience with IP integration or SOC integration
5. Experience in one or more of the following domains, is a plus
- High-Level Synthesis using SystemC
- Synopsys HAPS, Xilinx FPGA
- LPDDR
- AXI, AHB design
- Neural network
- Low power design
- USB, MIPI, sensor, display, peripherals
- Floorplan, package
2. 5+ years SOC design, verification, or related work experience.
3. Experience in digital IP design using Verilog or SystemVerilog.
4. Experience with several chip tapeout and mass production.
5. Specific experience with industry standard development tools is required.
6. Solid understanding of complete SOC design flow and design techniques and methods
Preferred qualifications:
1. Master's degree in Electrical Engineering or Computer Science.
2.Experience with architecture, specification definition, task force leading, project leading.
3. Experience with SOC flow building
4.Experience with IP integration or SOC integration
5. Experience in one or more of the following domains, is a plus
- High-Level Synthesis using SystemC
- Synopsys HAPS, Xilinx FPGA
- LPDDR
- AXI, AHB design
- Neural network
- Low power design
- USB, MIPI, sensor, display, peripherals
- Floorplan, package
工作地點
Taipei, Hsinchu