Senior Design Verification Engineer


1. Creating verification plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
2.  Create verification environments using SystemVerilog, SystemC or UVM.
3.  Identify and write all types of coverage measures for stimulus and corner-cases.
4.  Debug tests with design engineers to deliver functionally correct design blocks.
5.  Close coverage measures to identify verification holes and to show progress towards tape-out.


1. Bachelor's degree in Electrical Engineering or Computer Science.
2.  Experience in verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog or SystemC for ASICs and/or SoCs.
3. Experience with the creation of and usage of verification components and environments in a standard verification methodology such as UVM, OVM, or VMM.
4. Solid verification skills in problem solving, constrained random and directed tests, and debugging.
5. Be able to develop a SystemVerilog testbench from scratch.

Preferred qualifications:
1.  Master's degree in Electrical Engineering or Computer Science.
2.  5+ years experience in verification of complex SoC
3.  Solid understanding of complete SoC design flow and verification techniques and methods
4. Experience in one or more of the following application domains, is a plus
   - Defining coverage space and writing coverage model
   - Verification IP (VIP) development or usage
   - LPDDR
   - AMBA bus protocols
   - Verification using SystemC
   - Neural network


Taipei, Hsinchu