Senior Hardware Architect
We are looking for experienced RTL design and hardware architect who can define instruction set based on the target applications and algorithms, define hardware architecture forNeural-network Processing Unit (NPU) to optimize PPA, and implement hardware in systemCand apply high level synthesis to check PPA.
1. Define hardware architecture for NPU and DSP related sub-systems. Deliver quantative PPA analysis report for the architecture design. Deliver detailed hardware design specification for implementation.
2. Design hardware core blocks for Neural-network Processing Unit (NPU) and Digital-Signal-Processor(DSP) related sub-systems using system C; and apply high level synthesis to check PPA.
3. Synthesize RTL design based on 40nm/28nm/16nm stand-cell library to estimate power, area and clock frequency.
4. Design testbench and run behavior-level and clock-cycle accurate simulation using System-C.
5. Define hardware architecture for neural-network layer operations. Deliver system C codes to implement new neural-network model layer operations, such as concatenation, non-linear activation functions, branches, Region-of-Interest (RoI) pooling, etc.
6. Co-work with firmware, compiler, and model training team to optimize NPU/DSP performance
1. Extensive experience of RTL design
2. Real product experience of system C design and high level synthesis is a big plus.
3. Real product experience of NPU, DSP and/or GPU architecture design is a big plus.
3. Extensive experience of RTL block-level and system-level debugging
4. In-depth knowledge and experience in data-path and control logic design is a must.
5. Minimum 5 years industry experience with Master’s Degree in Electrical/Computer Engineering field
6. Ability to work independently with little or no supervision under tight schedules
7. Ability to quickly learn new technologies
8. Strong communication skills, including verbal, presentation, and documentation
1. Knowledge of ARM architecture and firmware programming
2. Knowledge of Neural-network model structure and algorithm