KL720 power pin decouping and filter

Dear Sir,

I have some questions regarding to power domain and power decoupling, filtering:

1/ If I do not use the USB 2.0 interface, Could I not supply power and decoupling capacitors for USB 2.0 power pins? Same for interface in bank 3?


2/ Using the Ferrit bead to isolate between power rails is needed, right? But Figure 3 - Power topology: KL720 bypass capacitors in the KL720 HW design guide v0.2, do not show the ferrite bead between power rails. Could you say me what is right/recommended?

In demo board design

Figure 3 - Power topology: KL720 bypass capacitors in the KL720 HW design guide v0.2

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